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FDB3652 / FDP3652 / FDI3652
April 2002
FDB3652 / FDP3652 / FDI3652
N-Channel UltraFET(R) Trench MOSFET 100V, 61A, 16m
Features
* r DS(ON) = 14m (Typ.), VGS = 10V, ID = 61A * Qg(tot) = 44nC (Typ.), VGS = 10V * Low Miller Charge * Low Qrr Body Diode * UIS Capability (Single Pulse and Repetitive Pulse) * Qualified to AEC Q101
Formerly developmental type 82769
Applications
* DC/DC Converters and Off-line UPS * Distributed Power Architectures and VRMs * Primary Switch for 24V and 48V Systems * High Voltage Synchronous Rectifier * Direct Injection / Diesel Injection Systems * 42V Automotive Load Control * Electronic Valve Train Systems
DRAIN (FLANGE) GATE SOURCE DRAIN GATE DRAIN (FLANGE)
SOURCE DRAIN GATE
D
SOURCE
G
TO-263AB
FDB SERIES
TO-220AB
FDP SERIES
DRAIN (FLANGE)
TO-262AA
FDI SERIES
S
MOSFET Maximum Ratings TC = 25C unless otherwise noted
Symbol VDSS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current Continuous (TC = 25oC, VGS = 10V) ID Continuous (TC = 100oC, VGS = 10V) Continuous (Tamb = 25oC, VGS = 10V) with RJA = 43oC/W) Pulsed E AS PD TJ, TSTG Single Pulse Avalanche Energy (Note 1) Power dissipation Derate above 25oC Operating and Storage Temperature 61 43 9 Figure 4 182 150 1.0 -55 to 175 A A A A mJ W W/oC
o
Ratings 100 20
Units V V
C
Thermal Characteristics
RJC RJA RJA Thermal Resistance Junction to Case TO-220, TO-263, TO-262 Thermal Resistance Junction to Ambient TO-220, TO-263, TO-262 (Note 2) Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area 1.0 62 43
o o o
C/W C/W C/W
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/ Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html. All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
(c)2002 Fairchild Semiconductor Corporation FDB3652 / FDP3652 / FDI3652 Rev. A
FDB3652 / FDP3652 / FDI3652
Package Marking and Ordering Information
Device Marking FDB3652 FDP3652 FDI3652 Device FDB3652 FDP3652 FDI3652 Package TO-263AB TO-220AB TO-262AA Reel Size 330mm Tube Tube Tape Width 24mm N/A N/A Quantity 800 units 50 units 50 units
Electrical Characteristics TC = 25C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V VDS = 80V VGS = 0V VGS = 20V TC= 150oC 100 1 250 100 V A nA
On Characteristics
VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250A ID = 61A, VGS = 10V rDS(ON) Drain to Source On Resistance ID = 30A, VGS = 6V ID = 61A, VGS = 10V, TJ = 175oC 2 0.014 0.018 0.035 4 0.016 0.026 0.043 V
Dynamic Characteristics
CISS COSS CRSS Qg(TOT) Qg(TH) Qgs Qgs2 Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge at 10V Threshold Gate Charge Gate to Source Gate Charge Gate Charge Threshold to Plateau Gate to Drain "Miller" Charge VDS = 25V, VGS = 0V, f = 1MHz VGS = 0V to 10V VGS = 0V to 2V VDD = 50V ID = 61A Ig = 1.0mA 2880 390 100 44 5.5 12.4 7 10 66 8.3 pF pF pF nC nC nC nC nC
Switching Characteristics (VGS = 10V)
tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time VDD = 50V, ID = 61A VGS = 10V, RGS = 6.8 12 85 26 45 146 107 ns ns ns ns ns ns
Drain-Source Diode Characteristics
VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 61A ISD = 30A ISD = 61A, dISD/dt = 100A/s ISD = 61A, dISD/dt = 100A/s 1.25 1.0 62 45 V V ns nC
Notes: 1: Starting TJ = 25C, L = 0.228mH, IAS = 40A. 2: Pulse Width = 100s
(c)2002 Fairchild Semiconductor Corporation
FDB3652 / FDP3652 / FDI3652 Rev. A
FDB3652 / FDP3652 / FDI3652
Typical Characteristics TC = 25C unless otherwise noted
1.2 75
POWER DISSIPATION MULTIPLIER
1.0 ID, DRAIN CURRENT (A) 0 25 50 75 100 125 150 175
0.8
50
0.6
0.4
25
0.2
0 TC , CASE TEMPERATURE (o C)
0 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs Ambient Temperature
2 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
Figure 2. Maximum Continuous Drain Current vs Case Temperature
ZJC, NORMALIZED THERMAL IMPEDANCE
PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 t , RECTANGULAR PULSE DURATION (s) 10-1 100 101
SINGLE PULSE 0.01 10-5 10-4
Figure 3. Normalized Maximum Transient Thermal Impedance
1000
TC = 25oC FOR TEMPERATURES TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 175 - TC 150 VGS = 10V
IDM, PEAK CURRENT (A)
100
50
10-5
10-4
10-3
10-2 t, PULSE WIDTH (s)
10-1
100
101
Figure 4. Peak Current Capability
(c)2002 Fairchild Semiconductor Corporation
FDB3652 / FDP3652 / FDI3652 Rev. A
FDB3652 / FDP3652 / FDI3652
Typical Characteristics TC = 25C unless otherwise noted
500 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 1/4 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] ID, DRAIN CURRENT (A) 125 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V
IAS, AVALANCHE CURRENT (A)
100
100 STARTING TJ = 25oC
75 TJ = 175o C 50 TJ = 25 oC 25 TJ = -55o C
10
STARTING TJ = 150oC
1 0.01 0.1 1 tAV, TIME IN AVALANCHE (ms) 10
0 3 4 5 6 VGS , GATE TO SOURCE VOLTAGE (V) 7
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 5. Unclamped Inductive Switching Capability
125 VGS = 10V 100 ID, DRAIN CURRENT (A) VGS = 6V 75 VGS = 7V DRAIN TO SOURCE ON RESISTANCE(m) 20
Figure 6. Transfer Characteristics
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 18 VGS = 6V
16
50
TC = 25oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
14 VGS = 10V 12
25 VGS = 5V 0 0 1 2 3 VDS , DRAIN TO SOURCE VOLTAGE (V) 4
0
20 40 ID, DRAIN CURRENT (A)
60
Figure 7. Saturation Characteristics
Figure 8. Drain to Source On Resistance vs Drain Current
1.4
3.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2.5 NORMALIZED GATE THRESHOLD VOLTAGE
VGS = VDS, ID = 250A 1.2
2.0
1.0
1.5
0.8
1.0
0.5 VGS = 10V, ID = 61A 0 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200
0.6
0.4 -80
-40
0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
200
Figure 9. Normalized Drain to Source On Resistance vs Junction Temperature
(c)2002 Fairchild Semiconductor Corporation
Figure 10. Normalized Gate Threshold Voltage vs Junction Temperature
FDB3652 / FDP3652 / FDI3652 Rev. A
FDB3652 / FDP3652 / FDI3652
Typical Characteristics TC = 25C unless otherwise noted
1.2 ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE CISS = CGS + CGD C, CAPACITANCE (pF) 1000 COSS CDS + CGD 5000
1.1
CRSS = CGD
1.0
100 VGS = 0V, f = 1MHz 0.9 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (o C) 200 40 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100
Figure 11. Normalized Drain to Source Breakdown Voltage vs Junction Temperature
10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 50V 8
Figure 12. Capacitance vs Drain to Source Voltage
6
4 WAVEFORMS IN DESCENDING ORDER: ID = 61A ID = 5A 0 10 20 30 Qg , GATE CHARGE (nC) 40 50
2
0
Figure 13. Gate Charge Waveforms for Constant Gate Currents
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0V RG IAS VDD VDD tP VDS
+
IAS 0.01 0 tAV
Figure 14. Unclamped Energy Test Circuit
Figure 15. Unclamped Energy Waveforms
(c)2002 Fairchild Semiconductor Corporation
FDB3652 / FDP3652 / FDI3652 Rev. A
FDB3652 / FDP3652 / FDI3652
Test Circuits and Waveforms (Continued)
VDS VDD L VGS VDS Qg(TOT) VGS
VGS = 10V
+
VDD DUT Ig(REF) VGS = 2V 0
Qgs2
Qg(TH) Qgs Ig(REF) 0 Qgd
Figure 16. Gate Charge Test Circuit
Figure 17. Gate Charge Waveforms
VDS
tON td(ON) RL VDS 90% tr
tOFF td(OFF) tf 90%
VGS
+
VDD DUT 0
10%
10%
RGS VGS VGS 0 10% 50% PULSE WIDTH
90% 50%
Figure 18. Switching Time Test Circuit
Figure 19. Switching Time Waveforms
(c)2002 Fairchild Semiconductor Corporation
FDB3652 / FDP3652 / FDI3652 Rev. A
FDB3652 / FDP3652 / FDI3652
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
(T -T ) JM A P D M = ----------------------------R JA
80 RJA = 26.51+ 19.84/(0.262+Area) EQ.2 RJA = 26.51+ 128/(1.69+Area) EQ.3 60 RJA (o C/W) 40 20 0.1 (0.645) 1 (6.45) AREA, TOP COPPER AREA in2 (cm2 ) 10 (64.5)
(EQ. 1)
In using surface mount devices such as the TO-263 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of P DM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 20 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 20 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeter square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. R JA
Figure 20. Thermal Resistance vs Mounting Pad Area
= 26.51 + ------------------------------------
19.84 ( 0.262 + Area )
(EQ. 2)
Area in Iches Squared
R
JA
= 26.51 + ---------------------------------
128 ( 1.69 + Area )
(EQ. 3)
Area in Centimeter Squared
(c)2002 Fairchild Semiconductor Corporation
FDB3652 / FDP3652 / FDI3652 Rev. A
FDB3652 / FDP3652 / FDI3652
PSPICE Electrical Model
.SUBCKT FDP3652 2 1 3 rev March 2002 Ca 12 8 1.1e-9 Cb 15 14 1.1e-9 Cin 6 8 2.8e-9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 108.2 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 7.16e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 2.29e-9 RLgate 1 9 71.6 RLdrain 2 5 10 RLsource 3 7 22.9 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 5.7e-3 Rgate 9 20 1.06 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 6.5e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*150),7))} .MODEL DbodyMOD D (IS=1.5E-11 N=1.06 RS=2.5e-3 TRS1=2.4e-3 TRS2=1.1e-6 + CJO=1.9e-9 M=5.8e-1 TT=2.5e-8 XTI=3.9) .MODEL DbreakMOD D (RS=2.7e-1 TRS1=1e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=7e-10 IS=1e-30 N=10 M=0.58) .MODEL MmedMOD NMOS (VTO=3.6 KP=5.5 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.06) .MODEL MstroMOD NMOS (VTO=4.3 KP=110 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=3 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.06e1 RS=.1) .MODEL RbreakMOD RES (TC1=1.05e-3 TC2=1e-6) .MODEL RdrainMOD RES (TC1=1.7e-2 TC2=3.2e-5) .MODEL RSLCMOD RES (TC1=1e-3 TC2=1e-7) .MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-5.3e-3 TC2=-1.2e-5) .MODEL RvtempMOD RES (TC1=-3.3e-3 TC2=1.3e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-8 VOFF=-5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5 VOFF=-8) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1 VOFF=0.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.5 VOFF=-1) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
CA S1A 12 13 8 S1B 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT 15 17 GATE 1 RLGATE CIN 10 RSLC1 51 ESLC 50 RDRAIN EVTHRES + 19 8 6 MSTRO LSOURCE 8 RSOURCE RLSOURCE RBREAK 18 RVTEMP 19 VBAT + 22 7 SOURCE 3 21 16 RLDRAIN DBREAK 11 + 17 EBREAK 18 MWEAK MMED LDRAIN DPLCAP 5 DRAIN 2
RSLC2
5 51 ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 -
(c)2002 Fairchild Semiconductor Corporation
+
DBODY
FDB3652 / FDP3652 / FDI3652 Rev. A
FDB3652 / FDP3652 / FDI3652
SABER Electrical Model
REV March 2002 template FDP3652 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=1.5e-11,nl=1.06,rs=2.5e-3,trs1=2.4e-3,trs2=1.1e-6,cjo=1.9e-9,m=5.8e-1,tt=2.5e-8,xti=3.9) dp..model dbreakmod = (rs=2.7e-1,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=7e-10,isl=10e-30,nl=10,m=0.58) m..model mmedmod = (type=_n,vto=3.6,kp=5.5,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.3,kp=110,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=3,kp=0.03,is=1e-30, tox=1,rs=.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-8,voff=-5) LDRAIN DPLCAP 5 sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-5,voff=-8) DRAIN 2 sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1,voff=0.5) 10 sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=-1) RLDRAIN RSLC1 c.ca n12 n8 = 1.1e-9 51 c.cb n15 n14 = 1.1e-9 RSLC2 c.cin n6 n8 = 2.8e-9 ISCL dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 108.2 spe.eds n14 n8 n5 n8 = 1 GATE 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.lgate n1 n9 = 7.16e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 2.29e-9 res.rlgate n1 n9 = 71.6 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 22.9
CA S1A 12 S1B 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 LGATE ESG + EVTEMP RGATE + 18 22 9 20 6 MSTRO CIN 8 6 8 EVTHRES + 19 8 50 RDRAIN 21 16 MWEAK MMED EBREAK + 17 18 DBREAK 11 DBODY
RLGATE
LSOURCE 7 RLSOURCE
SOURCE 3
RSOURCE RBREAK 18 RVTEMP 19
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=1.05e-3,tc2=1e-6 res.rdrain n50 n16 = 5.7e-3, tc1=1.7e-2,tc2=3.2e-5 res.rgate n9 n20 = 1.06 res.rslc1 n5 n51 = 1e-6, tc1=1e-3,tc2=1e-7 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 6.5e-3, tc1=1e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-5.3e-3,tc2=-1.2e-5 res.rvtemp n18 n19 = 1, tc1=-3.3e-3,tc2=1.3e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/150))** 7)) } }
(c)2002 Fairchild Semiconductor Corporation
FDB3652 / FDP3652 / FDI3652 Rev. A
FDB3652 / FDP3652 / FDI3652
SPICE Thermal Model
REV 23 March 2002 FDP3652 CTHERM1 TH 6 1e-2 CTHERM2 6 5 1.5e-2 CTHERM3 5 4 2e-2 CTHERM4 4 3 2.1e-2 CTHERM5 3 2 2.2e-2 CTHERM6 2 TL 9e-2
th
JUNCTION
RTHERM1
CTHERM1
6
RTHERM1 TH 6 2.7e-2 RTHERM2 6 5 2.8e-2 RTHERM3 5 4 7.8e-2 RTHERM4 4 3 9e-2 RTHERM5 3 2 2.7e-1 RTHERM6 2 TL 2.87e-1
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model FDP3652 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =1e-2 ctherm.ctherm2 6 5 =1.5e-2 ctherm.ctherm3 5 4 =2e-2 ctherm.ctherm4 4 3 =2.1e-2 ctherm.ctherm5 3 2 =2.2e-2 ctherm.ctherm6 2 tl =9e-2 rtherm.rtherm1 th 6 =2.7e-2 rtherm.rtherm2 6 5 =2.8e-2 rtherm.rtherm3 5 4 =7.8e-2 rtherm.rtherm4 4 3 =9e-2 rtherm.rtherm5 3 2 =2.7e-1 rtherm.rtherm6 2 tl =2.87e-1 }
RTHERM3 CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
(c)2002 Fairchild Semiconductor Corporation
FDB3652 / FDP3652 / FDI3652 Rev. A
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM FAST(R)
FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM I2CTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM OPTOLOGIC(R)
OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench(R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER (R) SMART STARTTM SPMTM
STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET(R) VCXTM
STAR*POWER is used under license
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. 2. A critical component is any component of a life support As used herein: device or system whose failure to perform can be 1. Life support devices or systems are devices or systems reasonably expected to cause the failure of the life support which, (a) are intended for surgical implant into the body, device or system, or to affect its safety or effectiveness. or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Preliminary
No Identification Needed
Full Production
Obsolete
Not In Production
FDB3652 / FDP3652 / FDI3652 Rev. H5

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